1. Field of the Invention
The present invention relates to the field of high speed CMOS current switching circuits, such as current sources and the like.
2. Prior Art
It is well known to use current steering circuits for supplying and selectively directing currents to one or more outputs. One use of such steering circuits is in digital to analog converters in graphic interfaces wherein a plurality of such current steering circuits are used to selectively supply current components to a resistor to convert multiple bit digital signals to corresponding analog signals for direct input to an RGB monitor. In such applications, one or both of two requirements may be particularly important. In particular, in high resolution displays, the pixel rate will be particularly high. In addition, it is desirable to have as much of the pixel time as possible to represent the true analog value of a digital signal, and as little of the pixel time as possible devoted to the rise and fall times of a respective analog signal. Accordingly, speed of operation of the digital to analog converters and thus of the current steering circuits for each bit of the digital signal is of particular importance in such applications.
Also, in portable computers, power consumption is an important consideration. Consequently, while a current steering circuit must provide the required current to the load when the corresponding bit of the multi-bit digital signal being converted is a 1, it is highly desirable for the current steering circuit to draw minimal current (power) when a respective input bit thereto is a 0. Accordingly, it is highly desirable to maximize the operating speed and minimize the current requirements of such current steering circuits in applications such as digital to analog converters for graphic interfaces so as to make the same devices useful in high resolution graphic applications, low power consumption applications and/or both such applications.
In U.S. Pat. No. 4,831,282, a CMOS circuit is disclosed comprising three P-channel MOS devices. As shown in FIG. 1 of that patent, the source of the first device is connected to +5 volts and its gate is connected to a circuit so as to establish a gate-source voltage in the first device to provide a fixed, predetermined current through the device. The drain of the first device is connected to a node common with the sources of the second and third devices, with the drain of the second device providing the output current and the drain of the third device being connected to ground. The gate of the second device is held at a reference voltage so that when the gate of the third device is high (higher than the reference voltage on the gate of a second device), the third device will be off and the node will assume a voltage to establish a gate-source voltage across the second device to turn the device on just enough to conduct the fixed current through the first device to the circuit output. When the gate of the third device is low, the third device is turned on, pulling the node lower in voltage to establish the gate-source voltage in the third device to conduct the current through the first device to ground, thereby lowering the gate-source voltage of the second device to turn off the current flow to the output.
In essence, the foregoing circuit establishes a known current source through the first device, and either steers that current to ground or to the output. As such, the circuit is relatively simple and is stated in the '282 patent to "operate satisfactorily at frequencies in excess of 85 megahertz (85 MHz)." It has the disadvantage, however, of consuming a fixed amount of power per bit regardless of the input, as the same current is provided, independent of whether the bit is a 1 and the current is directed or steered to the output, or the bit is a 0 and the current is steered to ground.
In U.S. Pat. No. 5,179,292, CMOS circuits are disclosed which utilize four P-channel devices. In particular, in place of the single first device of the '282 patent, two devices in parallel are provided, one to establish a relatively small constant idle current and the other to provide a multiple of the idle current (such as, by way of example, fifteen times the idle current) upon the occurrence of the input bit being a 1. Thus, the idle current, normally directed to ground by one of the lower devices, establishes the node voltage, and only when a 1 bit is provided to the circuit is the current to the node increased to provide the full predetermined output current as desired. Accordingly, the power consumption of this circuit can be substantially less than in the circuit of the '282 patent because of its not consuming substantial power for 0 bit value inputs.
There is an advantage in being able to provide current switching circuits for use in graphic controller digital to analog converters which are of even higher speed and of low power consumption for high resolution and for battery operated computers. In that regard, it is desirable to minimize power consumption in all computers to allow closer component packing, smaller power supplies and lower operating temperatures with passive cooling as computers continue to become smaller and processing capability increases.
It is also desirable to provide low power current steering circuits which can perform dynamic current steering without affecting switching speed performance.